Minimizing the leakage power consumption and improving the reliability of memory arrays such as static random access memory (SRAM) arrays are among current design challenges of microprocessors with large on-die caches. One source of leakage power is associated with the bitlines. Traditionally, the bitlines of such arrays are precharged to full Vcc when the arrays are not accessed or in sleep mode. However, this bitline precharging is associated with various problems including power leakage, as well as other less recognized issues relevant to design limitations.
Conventional techniques for addressing the leakage problem include reducing the bitline voltage, by using n-channel metal oxide semiconductor (NMOS) and p-channel metal oxide semiconductor (PMOS) prechargers in combination, which effectively limit the bitlines at a threshold voltage drop from Vcc when the arrays are not accessed. However, such conventional techniques tend to significantly increase design overhead and generally provide inadequate leakage reduction. What is needed, therefore, are techniques for power conservation for integrated circuit memories.